Steven M. Nowick

PROFESSOR OF COMPUTER SCIENCE; PROFESSOR OF ELECTRICAL ENGINEERING

508 Computer Science Building
Mail Code 0401

Tel(212) 939-7056
Fax(212) 666-0140

Steven M. Nowick’s research is on developing asynchronous and mixed synchronous-asynchronous digital systems.  Asynchronous design has recently demonstrated the potential to offer significant improvements in performance, energy and reliability, since it eliminates the rigidity of the traditional fixed-rate synchronous clock, allowing flexible and scalable assembly of complex computer systems.   His work spans the areas of on-chip interconnection networks for high-performance parallel computers and low-energy embedded systems, ultra-low-energy digital design, fault-tolerant and resilient hardware, and applications to emerging technologies.

Research Interests

Asynchronous and mixed-timing digital systems, scalable high-performance and low-power on-chip networks for parallel processors and embedded systems, computer-aided digital design (CAD), ultra-low-energy digital systems,, variation-tolerant global communication.

Research Areas

Of particular interest to Nowick is the design of efficient networks-on-chip (NoCs), which are becoming the standard for organizing communication in complex many-core computers (i.e. with hundreds or thousands of processors, memories, and other components), as well as for use in emerging neuromorphic (i.e. “brain-inspired”) parallel processors.  He has developed low-latency and energy-efficient routers for asynchronous NoCs, which have been recently been deployed experimentally at AMD Research.  His research also includes high-performance asynchronous pipeline designs, as well as robust interfaces between different clock domains and to support boundary crossings between the asynchronous and synchronous digital realms.  He has also developed efficient digital coding schemes for variation-tolerant and reliable communication. 

Nowick received a BA from Yale University in 1976 and a PhD in computer science from Stanford University in 1993.   He is a fellow of the Institute of Electrical and Electronics Engineers (IEEE), a senior member of the Association for Computing Machinery (ACM), and an Alfred P. Sloan Research Fellow.  He is also the recipient of NSF CAREER and RIA awards. 

PROFESSIONAL EXPERIENCE

  • Chair/Founder, “Frontiers in Computing Systems” Working Group, Data Science Institute, Columbia University, 2016-
  • Professor of Computer Science, Columbia University, 2008-
  • Chair, Computer Engineering Program, Columbia University, 2008-2013
  • Associate Professor of Computer Science, Columbia University, 1998-2008
  • Co-Founder, Computer Engineering Program, Columbia University, 1994
  • Assistant Professor of Computer Science, Columbia University, 1993-1998

PROFESSIONAL AFFILIATIONS

  • Association for Computing Machinery (ACM)
  • Institute of Electrical and Electronics Engineers (IEEE)

HONORS & AWARDS

  • SEAS Alumni Distinguished Faculty Teaching Award, 2011
  • Fellow, Institute of Electrical and Electronics Engineers (IEEE), 2009
  • Senior Member, Association for Computing Machinery (ACM), 2009
  • Alfred P. Sloan Research Fellowship, 1995
  • NSF Faculty Early Career Development (“CAREER”) Award, 1995
  • NSF Research Initiation Award (“RIA”), 1993
  • Best Paper Award, IEEE International Conference on Computer Design (logic & circuit design track), 2012
  • Best Paper Award, IEEE “Async” Symposium, 2000
  • Best Paper Award, IEEE International Conference on Computer Design (computer-aided design track), 1991

GRANT SUPPORT

  • NSF Grant: “SHF:Small: An Asynchronous Network-on-Chip Methodology for Cost-Effective and Fault-Tolerant Heterogeneous SoC Architectures,” PI: S.M. Nowick. NSF Award No. CCF-1527796 (8/1/15-7/31/18). 
  • NSF Grant: “SHF:Small: Designing Low-Latency and Robust Interconnection Networks with Fine-Grain Dynamic Adaptivity Using Asynchronous Techniques,” PI: S.M. Nowick. NSF Award No. CCF-1219013 (7/1/12-6/30/16).
  • NSF Medium-Scale Award: SHF:Medium: Power-Adaptive, Event-Driven Data Conversion and Signal Processing Using Asynchronous Digital Techniques,” PI: Y. Tsividis (Columbia EE Dept.), co-PI: S.M. Nowick. NSF Award No. CCF-0964606 (7/1/10-6/30/15).   
  • NSF Medium-Scale Award: “CPA-DA-T: Design and Tools for Easy-to-Program Massively Parallel On-Chip Systems: Deriving Scalability Through Asynchrony,” PI: S. Nowick, co-PI: U. Vishkin (U. of Maryland). NSF Award No. CCF- 0811504 (8/1/08-7/31/13).   
  • DARPA “CLASS” Project, subcontract under Boeing Corporation (2005-2007). 
  • NSF Grant: “Methodologies and CAD Tools for the Design of Asynchronous Systems,” PI: S. Nowick. NSF Award No. CCR-99-88241 (11/15/00-10/31/03)
  • NSF Medium-Scale ITR Award: “A CAD Framework for the Design and Optimization of Large-Scale Asynchronous Digital Systems”. PI: S. Nowick (joint proposal with University of Southern California). NSF Award No. CCR-00- 86036 (9/1/00-8/31/05).   
  • NSF Medium-Scale ITR Award: “Asynchronous Digital Signal Processing for the Software Radio”. co-PI: S. Nowick (joint proposal with Prof. Ken Shepard, EE Department). NSF Award No. CCR-00-86007 (9/1/00-8/31/03). 
  • NYS Center for Advanced Technology (CAT): “The Design of Multi-Gigahertz Asynchronous Arithmetic 

SELECTED PUBLICATIONS

  • W. Jiang, D. Bertozzi, G. Miorandi, S.M. Nowick, W. Burleson and G. Sadowski, “An Asynchronous NoC Router in a 14nm FinFET Library: Comparison to an Industrial Synchronous Counterpart.” In Proceedings of the ACM/IEEE Design, Automation and Test in Europe Conference (DATE-17), Lausanne, Switzerland (March 2017). 
  • K. Bhardwaj and S.M. Nowick, “Achieving Lightweight Multicast in Asynchronous Networks-on- Chip Using Local Speculation.” In Proceedings of the ACM/IEEE Design Automation Conference (DAC-16), Austin, TX (June 2016). 
 

  • S.M. Nowick and M. Singh, “Asynchronous Design – Part 1: Overview and Recent Advances.” IEEE Design and Test, vol. 22:3, pp. 5-18 (May/June 2015). 

  • C. Vezyrtzis, W. Jiang, S.M. Nowick and Y. Tsividis, “A Flexible, Event-Driven Digital Filter with Frequency Response Independent of Input Sample Rate.” IEEE Journal of Solid-State Circuits, vol. 49:10, pp. 2292-2304 (October 2014).
  • A. Ghiribaldi, D. Bertozzi and S.M. Nowick, “A Transition-Signaling Bundled Data NoC Switch Architecture for Cost-Effective GALS Multicore Systems.” In Proceedings of the ACM/IEEE Design, Automation and Test in Europe Conference (DATE-13), Grenoble, France (March 2013). 

  • S.M. Nowick and M. Singh, “High-Performance Asynchronous Pipelines: an Overview.” IEEE De- sign and Test of Computers, vol. 28:5, pp. 8-22 (September/October 2011). 

  • M.N. Horak, S.M. Nowick, M. Carlberg and U. Vishkin, “A Low-Overhead Asynchronous Intercon- nection Network for GALS Chip Multiprocessors.” IEEE Transactions on Computer-Aided Design, vol. 30:4, pp. 494-507 (April 2011). 

  • M. Singh and S.M. Nowick, “MOUSETRAP:  High-Speed Transition-Signaling Asynchronous Pipelines.” IEEE Transactions on VLSI Systems, vol. 15:6, pp. 684-698 (June 2007). 

  • T. Chelcea and S.M. Nowick, “Robust Interfaces for Mixed-Timing Systems.” IEEE Transactions on VLSI Systems, vol. 12:8, pp. 857-873 (August 2004). 

  • S.M. Nowick and D.L. Dill, “Exact Two-Level Minimization of Hazard-Free Logic with Multiple- Input Changes.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14:8, pp. 986-997 (August 1995).