Charles Zukowski | Plugging the Leak in Circuit Efficiency
Professor of Electrical Engineering
This profile is included in the publication Excellentia, which features current research of Columbia Engineering faculty members.
Photo by Eileen Barroso
Computer chips are the building blocks that allow billions of transistors to fit in a small area. These chips have enhanced everyday life, and enable the design of electronics of increasing functionality and lower cost, making most modernday technology possible. But as transistors continue to become smaller and faster, new challenges for circuit designers constantly arise. The research field of Very Large Scale Integration (VLSI) addresses these challenges.
One of those challenges is transistor current leakage, which is becoming a bigger problem as transistors in computer chips continue to shrink, leading to problems with power and reliability. While current leakage and power dissipation in each transistor remain quite small, they can add up to a significant amount over billions of transistors, potentially limiting function and performance.
Solving this problem could have a big impact on industry, and the feasibility of critical future applications of electronics.
Charles Zukowski, past chairman and current vice chairman of the Department of Electrical Engineering, has worked in the area of VLSI throughout his career and has contributed to the progress of integrated circuit technology in a number of areas. His chief focus now is twofold: circuit techniques such as monotonic logic to reduce the impact of current leakage in future integrated circuit technologies; and special-purpose hardware prototypes for the simulation of gene regulatory networks.
Through this work, his intention is to further the capability of integrated circuit technology and to explore new applications.
His research has covered both circuit design and circuit analysis, results of which include a patented circuit technique for generating high data-rate serial data from a number of lower data-rate channels, and an approach for mixing digital and large-signal analog computation for simulation. He derived a number of results for bounding the behavior of digital integrated circuits that were compiled into a research monograph, and based on this work, he received a National Science Foundation Presidential Young Investigator Award.
He later developed a technique for measuring the convergence of waveform relaxation algorithms for simulating digital circuits. He also proposed a technique for significantly reducing the power consumption in certain content-addressable memories and investigated the use of various memories and circuit techniques in internet routing hardware. Throughout, he has consulted for industry in the field of Complementary Metal Oxide Semiconductor Integrated Circuit (CMOS IC) design.
B.S., Massachusetts Institute of Technology, 1982; M.S., MIT, 1982; Ph.D., MIT, 1985